Wireless data signals are frequently transmitted over hostile radio frequency (RF) interfaces that are susceptible to errors from interference. Thus many types of error correction coding techniques have been created to overcome such interference-induced signal errors. Error correction coding enables the recovery of an original clean signal from a corrupted signal. Turbo codes are advanced wireless error correction coding schemes that are included in many third generation wireless communication standards.
Turbo decoders perform soft-input, soft-output (SISO) operations that exchange information cooperatively to produce accurate estimates of transmitted data that is received over a noisy communication channel. The estimates are defined as probabilities and are interleaved and deinterleaved between SISO operations. Such interleaving scrambles the processing order of received data symbols so as to break up any neighborhoods of corrupted data.
The SISO operations of turbo decoders are executed using iterative decoding algorithms that increase the processing complexity of turbo decoders. To decode an input data stream at the same frequency at which data are arriving, a turbo decoder must process the data at a rate that is faster than the frequency of the arriving data by a factor at least equal to the number of iterations required by the decoder. Thus the speed of a decoder processor is very important to ensure a high quality of service (QoS) to an end user.
To increase processing speed turbo decoders generally divide an incoming block of data into sub-blocks. The sub-blocks are then processed in parallel using multiple sub-decoders. Each sub-decoder implements a Log Maximum-A-Posterior (MAP) algorithm that performs the SISO operations. The output of the Log MAP algorithms are named Log Likelihood Ratios (LLRs) and, concerning digital data, represent the probability that an originally transmitted data bit was either a “0” or a “1”.
To perform efficiently, it is critical that the sub-decoders operating in parallel do not interfere with each other, both when reading input data and when storing output data. If the interleavers of a turbo decoder are not designed properly, two sub-decoders may attempt to access the same extrinsic memory bank during a given clock cycle—resulting in what is known as a collision or memory contention. Thus interleavers must be designed so that each sub-decoder will always access a distinct memory bank at any given instant.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.